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Journal of Applied Physics / Volume 110 / Issue 12 / ARTICLES / Device Physics

J. Appl. Phys. 110, 124507 (2011); http://dx.doi.org/10.1063/1.3660697 (9 pages)

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Abhijeet Paul1, Giuseppe C. Tettamanzi2, Sunhee Lee1, Saumitra R. Mehrotra1, Nadine Collaert3, Serge Biesemans3, Sven Rogge2, and Gerhard Klimeck1

1School of Electrical and Computer Engineering, Network for Computational Nanotechnology, Purdue University, West Lafayette, Indiana 47907, USA
2Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, 2628 CJ Delft, The Netherlands and Centre for Quantum Computation and Communication Technology, University of New South Wales, Sydney, New South Wales 2052, Australia
3IMEC, 3001 Leuven, Belgium

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(Received 19 February 2011; accepted 14 October 2011; published online 20 December 2011)

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical tight-binding (TB) calculations, this technique can be used to understand the dependence of the source-to-channel barrier height (Eb) and the active channel area (Saa) on three important parameters: (i) the gate bias (Vgs), (ii) the temperature, and (iii) the FinFET cross-section size. The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) Saa and (ii) |∂Eb/∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nanometer width limit. Furthermore, theoretical investigation of the spatial current density reveals volume inversion in thinner FinFETs near the threshold voltage.

© 2011 American Institute of Physics

Article Outline

  1. INTRODUCTION
  2. DEVICE AND EXPERIMENTAL DETAILS
  3. MODELING APPROACH
    1. Self-consistent calculation
    2. Calculation of Eb and Saa
  4. TRAP EXTRACTION METHODS
    1. Method I: Dit from active area
    2. Method II: Dit from barrier control
    3. Limitations of the methods
  5. RESULTS AND DISCUSSION
    1. 3D versus 1D system
    2. Temperature dependence of Eb
    3. Evolution of Eb and Saa with Vgs
    4. Trap density evaluation
      1. D it using S AA : Method I
      2. D it using |∂E b /∂V gs |: Method II
      3. Discussion on the two methods and D it trends
    5. Current distribution
  6. CONCLUSIONS

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KEYWORDS and PACS

Keywords

current density, electric admittance measurement, electron mobility, elemental semiconductors, interface states, MOSFET, silicon, tight-binding calculations

PACS

ARTICLE DATA

Digital Object Identifier
http://dx.doi.org/10.1063/1.3660697

PUBLICATION DATA

ISSN

0021-8979 (print)  
1089-7550 (online)

Publisher

$abstract.society.value is a Member of CrossRef American Institute of Physics

For access to fully linked references, you need to log in.
    T. B. Boykin, G. Klimeck, and F. Oyafuso, Phys. Rev. B 69, 115201 (2004).

    M. Luisier, A. Schenk, W. Fichtner, and G. Klimeck, Phys. Rev. B 74, 205323 (2006).

    R. Kim, C. Jeong, and M. S. Lundstrom, J. Appl. Phys. 107, 054502 (2010)JAPIAU000107000005054502000001.


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